Implementation of High Speed Low Power Split-SAR ADCS Using Vcm and Capacitor Based Switching

This paper analyzes the parasitic effects in SAR ADCs. Successive approximation technique in ADC is well known logic, where in the presented design the linearity analysis of a Successive Approximation Registers (SAR) Analog-to-Digital Converter (ADC) with split DAC structure based on two switching methods: VCM -based switching, Switch to switchback process. The main motivation is to implement design of capacitor array DAC and achieve high speed with medium resolution using 45nm technology. The other advantage is matching of capacitor can be achieved better then resistor. This is verified by behavioural Measurement results of power, speed, resolution, and linearity clearly show the benefits of using VCM -based switching. In the proposed design the SAR ADC is designed in switch to switchback process such a way that the control module completely control the splitting up of modules, and give an option to change the speed of operation using low level input bits. A dedicated multiplexer is designed for that purpose system.